The present invention relates, in general, to semiconductor devices, and more particularly, to a novel bipolar transistor.
In the past, the semiconductor industry has produced complementary metal oxide semiconductor (CMOS) transistors along with bipolar PNP and NPN transistors on a single substrate. The combination of transistor types is often referred to as BICMOS. Vertical bipolar PNP transistors that are formed as part of a BICMOS device typically are formed in a P-type well that is isolated from other transistors on the BICMOS device by P-N junctions. A heavily doped region usually extends laterally across the entire P-type well in order to form a low resistance collector region for the transistor. This P-type well generally is formed in a thick epitaxial layer (typically thicker than 2.0 microns) in order to provide sufficient room within the epitaxial layer to form this low resistance collector region while allowing sufficient space to form a base above the collector. The thick epitaxial layer has the disadvantage of degrading the performance of NPN bipolar transistors by increasing the NPN transistor's vertical collector resistance and transit time. In addition, the PNP transistor's low resistance collector region occupies a large area that creates a large parasitic collector capacitance (usually greater than 950 femtofarads) thereby degrading the PNP transistor' s performance.
Accordingly, it is desirable to have a PNP transistor that is formed on a thin epitaxial layer (less than 2.0 microns thick), that has a low collector resistance, that has a low collector capacitance (less than 950 femtofarads), and that does not limit the performance of NPN transistors.